1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for forming a MOS transistor with a silicide layer formed on the gate conductor without concurrent formation of silicide on the source and drain regions.
2. Description of the Related Art
The fabrication of a metal-oxide semiconductor ("MOS") transistor is well known in the art of semiconductor processing. As the transistor dimensions of integrated circuits decrease, the sheet resistivity of the shallow junctions of the lightly doped drain ("LDD") regions increases. To reduce these resistance values, a silicide is typically formed over these regions. Additionally, it is also important to reduce the interconnect resistance of the polysilicon gate to the interconnect lines. Reduction of the interconnect resistance typically decreases the RC time delays, thus increasing the performance of the integrated circuit. A procedure which simultaneously reduces the resistance values of the source/drain regions, as well as the interconnect resistance of the gate conductor, is known as a self-aligned silicide ("salicide") procedure. A salicide procedure involves depositing a metal over a MOS transistor and reacting the metal with any exposed silicon-based areas to form silicide portions. Following silicide formation, a selective etch removes the unreacted metal without attacking the silicide.
FIG. 1 depicts a typical MOS conductor after salicidation of the exposed silicon surfaces. Typically, a refractory metal is deposited over the semiconductor topography. A variety of refractory metals may be used, including, but not limited to, tungsten, titanium, tantalum, cobalt, and molybdenum. After deposition of the refractory metal the MOS transistor is subjected to an anneal process. The anneal process preferably causes the growth of silicide layers 60 and 62 over the source/drain 44 and gate conductor regions 30, respectively. Note that the spacers 50 are used to prevent silicide from forming along the walls of the gate conductor. This typically prevents the gate and the source/drain regions from becoming electrically connected. After the silicide formation is complete, all non-reacted metal is removed.
The salicide process has the limitation that the gate and the source/drain silicides are formed at the same time. For most devices, it is desirable that a silicide layer is formed on the gate, thus allowing the gate to have the lowest possible interconnect resistance. However, in some devices, it is undesirable that a silicide is formed on the source/drain regions. For example, many flash EPROM devices incorporate resistors within the source and/or drain regions. In order to operate per design, the resistance value of these devices may need to be quite high. If a silicide is formed in a highly resistive source or drain area, the EPROM device may be rendered inoperable. Another problem associated with silicide formation on the source and/or drain areas may relate to diffusion problems. For example, it is known that some refractory metals readily diffuse into the source and/or drain regions during salicide formation. This diffusion tends to lead to spiking through the junction, causing substantial leakage problems.
One method to overcome the above problem involves the selective etching of a deposited silicide layer. Typically, a refractory metal silicide is deposited over the source/drain regions, as well as the polysilicon layer, prior to the formation of the gate conductor. A masking step must therefore be used, whereby the regions where the silicide is desired are masked using standard photolithographic techniques. The unmasked portions of the silicide are typically etched, leaving silicide in the desired locations. Typically, tungsten silicide (WSi.sub.2) is used for such a procedure, even though it has a higher resistance than other metal silicides (e.g., titanium silicide, TiSi.sub.2). Titanium silicide is typically not used because, although it is desirable for its low resistance, it is much more difficult to etch than WSi.sub.2. In addition, this process may suffer from alignment problems as the size of the transistors drops to sub-micron levels.
It is therefore desirable to devise a process by which a self-aligned silicidation of the gate structures may be accomplished without the concurrent silicidation of the source/drain regions. It is further desirable that such a process involves a minimal number of additional steps. It is still further desired that the process be applicable to low resistance refractory metal silicides (e.g., TiSi.sub.2) defined exclusively to the gate conductor.